A CMOS mixed-signal integrated circuit having a reduced vector set and closed-loop analog test architecture

Author

Chavan, A.V. ; String, D.W. ; Mallarapu, S.R. ; Ardeishar, R.

Author_Institution

Delco Electron. Corp., Kokomo, IN, USA

fYear

1996

fDate

5-8 May 1996

Firstpage

471

Lastpage

474

Abstract

This paper describes a mixed-signal IC that employs a test architecture consisting of multiple selectable sub-scan chains (SSCs), which the authors have termed “pseudo full scan”. This implementation reduces test pattern length and improves fault grading. An additional scan chain of boundary shift register latches (BSRLs) is used to sensitize the analog section of the IC to permit closed-loop testing. A mixed-signal IC using this architecture can be tested with a less expensive digital IC tester. Modeling for standard automatic test pattern generation (ATPG) tools is also presented

Keywords

CMOS integrated circuits; automatic testing; design for testability; integrated circuit design; integrated circuit testing; mixed analogue-digital integrated circuits; ATPG tools; CMOS mixed-signal IC; DFT; automatic test pattern generation; boundary shift register latches; closed-loop analog test architecture; fault grading improvement; multiple selectable sub-scan chains; pseudo full scan; reduced vector set; test pattern length reduction; Analog integrated circuits; Automatic test pattern generation; CMOS analog integrated circuits; Circuit faults; Circuit testing; Digital integrated circuits; Electronic equipment testing; Integrated circuit testing; Mixed analog digital integrated circuits; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Conference_Location

San Diego, CA

Print_ISBN

0-7803-3117-6

Type

conf

DOI

10.1109/CICC.1996.510599

Filename

510599