DSP16000: a high performance, low-power dual-MAC DSP core for communications applications

Author

Alidina, M. ; Burns, G. ; Holmqvist, C. ; Morgan, E. ; Rhodes, D. ; Simanapalli, S. ; Thierbach, M.

Author_Institution

Bell Labs., Lucent Technol., Allentown, PA, USA

fYear

1998

fDate

11-14 May 1998

Firstpage

119

Lastpage

122

Abstract

We present Lucent Technologies´ first dual-MAC DSP core. The 16-bit, fixed-point device features a datapath with two 16×16-bit multipliers and dual 40-bit adders that can all operate in one clock cycle to support compute-intensive DSP algorithms. In addition, the device includes special hardware to support all aspects of key communications applications such as wireless terminals, wireless infrastructure, and multichannel modems. The architecture offers a solution for these applications that balances performance, cost and power dissipation

Keywords

adders; digital signal processing chips; fixed point arithmetic; low-power electronics; mobile communication; modems; multiplying circuits; 16 bit; DSP16000; adders; clock cycle; compute-intensive DSP algorithms; datapath; fixed-point device; low-power dual-MAC DSP core; multichannel modems; multipliers; power dissipation; wireless infrastructure; wireless terminals; Arithmetic; Clocks; Computer architecture; Control systems; Costs; Digital signal processing; Hardware; Modems; Power dissipation; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-4292-5

Type

conf

DOI

10.1109/CICC.1998.694919

Filename

694919