Scan paths through functional logic

Author

Chih-chang Lin ; Marek-Sadowska, M. ; Kwang-Ting Cheng ; Lee, M.T.C.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA

fYear

1996

fDate

5-8 May 1996

Firstpage

487

Lastpage

490

Abstract

Conventional scan design imposes considerable area and delay overhead due to the use of larger flip-flops and additional connections between flip-flops. We propose a low-overhead scan design methodology which exploits the possibility of utilizing input vectors and the test-mode point insertion technique to establish scan paths through the combinational logic. The technique re-uses the existing functional logic; as a result, the DFT overhead can be reduced.

Keywords

automatic testing; boundary scan testing; delays; design for testability; flip-flops; integrated circuit testing; logic testing; sequential circuits; ATPG; DFT overhead; area overhead; combinational logic; delay overhead; flip-flops; functional logic; input vectors; low-overhead scan design methodology; scan paths; sequential circuits; test-mode point insertion technique; Automatic test pattern generation; Circuit synthesis; Circuit testing; Controllability; Design for testability; Design methodology; Flip-flops; Logic design; Logic testing; Observability;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Conference_Location

San Diego, CA, USA

Print_ISBN

0-7803-3117-6

Type

conf

DOI

10.1109/CICC.1996.510603

Filename

510603