Optimization of standard cell libraries for low power, high speed, or minimal area designs

A methodology for optimization of device sizes in CMOS standard cell libraries is described. The libraries are generated by compilers that allow for design rule and device size parameterization. Device sizes are optimized to achieve a low power, high speed, or minimal layout area cell library. The device sizing algorithms have been exercised on more than 80 different processes from 25 silicon foundries. This paper describes the three sizing algorithms and presents cell performance data and results from standard cell designs implemented with the three cell libraries