Scaling issues in the evolution of ExCL bipolar technology

Author

Brighton, J.E. ; Verret, O.P. ; Eyck, T. T Ten ; Welch, M.T. ; McMann, R.E. ; Torreno, M.L. ; Appel, A.T. ; Keleher, M.P.

Author_Institution

Texas Instrum. Inc., Houston, TX, USA

fYear

1988

fDate

12-13 Sep 1988

Firstpage

121

Lastpage

124

Abstract

Several issues encountered in scaling ExCL technology are discussed. It is shown that doping profile scaling below 0.15 μm base width puts severe restrictions on process latitude. It is demonstrated that the polysilicon emitter resistance can be significantly reduced by rapid thermal annealing. Capacitance calculations show that interconnect-related parasitics do not scale below 3 μm pitch, and intralevel coupling may provide the ultimate limitation of interconnect scaling. Finally, the ExCL metallization scheme is proven to be scalable to 2 μm metal pitch

Keywords

VLSI; bipolar integrated circuits; capacitance; doping profiles; emitter-coupled logic; incoherent light annealing; integrated circuit technology; metallisation; ExCL bipolar technology; base width; capacitance; doping profile scaling; interconnect scaling; interconnect-related parasitics; intralevel coupling; metallization scheme; pitch; polysilicon emitter resistance; rapid thermal annealing; scaling; Bipolar transistors; Breakdown voltage; Capacitance; Circuit optimization; Contact resistance; Doping profiles; Electric resistance; Integrated circuit interconnections; Isolation technology; Rapid thermal annealing;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1988., Proceedings of the 1988

Conference_Location

Minneapolis, MN

Type

conf

DOI

10.1109/BIPOL.1988.51061

Filename

51061