• DocumentCode
    2216657
  • Title

    CMOS-year 2010 and beyond; from technological side

  • Author

    Iwai, Hiroshi

  • Author_Institution
    Toshiba Corp., Kawasaki, Japan
  • fYear
    1998
  • fDate
    11-14 May 1998
  • Firstpage
    141
  • Lastpage
    148
  • Abstract
    CMOS LSIs, having advanced remarkably during the past 25 years, are expected to continue to progress well into the next century. The progress has been driven by the downsizing of the components in an LSI, such as MOSFETs. However, even before the downsizing of MOSFETs reaches its fundamental limit, the downsizing is expected to encounter severe technological and economic problems at the beginning of next century when the minimum feature size of LSIs is going to shift to 0.1 and sub-0.1 μm. In this paper, the anticipated difficulties and some concepts for 0.1 and sub-0.1 μm LSIs are explained based on the research of the downsizing MOSFET into such dimension, and further concept for deepsub-0.1 μm LSIs is described
  • Keywords
    CMOS integrated circuits; MOSFET; integrated circuit design; integrated circuit technology; large scale integration; 0.1 micron; CMOS LSI; MOSFET downsizing; minimum feature size; CMOS technology; Calculators; Costs; Cultural differences; Economics; Large scale integration; MOSFETs; Microprocessors; Personal communication networks; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
  • Conference_Location
    Santa Clara, CA
  • Print_ISBN
    0-7803-4292-5
  • Type

    conf

  • DOI
    10.1109/CICC.1998.694924
  • Filename
    694924