DocumentCode
2216883
Title
Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications
Author
Wang, Zhong ; Kirkpatrick, Michael ; Sha, Edwin Hsing-Mean
Author_Institution
University of Notre Dame
fYear
2000
fDate
2000
Firstpage
540
Lastpage
545
Keywords
Central Processing Unit; Computer architecture; Delay; Digital signal processing; Memory management; Modems; Partitioning algorithms; Prefetching; Processor scheduling; Scheduling algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2000. Proceedings 2000
Print_ISBN
1-58113-187-9
Type
conf
DOI
10.1109/DAC.2000.855370
Filename
855370
Link To Document