Title :
A new optimization strategy for CMOS device process in the era of 0.2 μm and beyond for MPU´s and ASIC´s
Author :
Mori, Kazutaka ; Kikushima, Ken´ichi ; Ootsuka, Fumio ; Mitani, Shin´ichiro
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Abstract :
A guideline of CMOS device development for high performance MPU´s and ASIC´s is discussed. The thermal runaway is found to limit lowest V TH. A new scaling rule including long metal wires is discussed, including effectiveness of optional wide lines and line-repeaters. “Wiring Channel Density”, which shows the process capability of high integration, is proposed. Based on the guideline, a manufacturable 0.2 μm CMOS device with 7-layer metal is designed. It shows 1.5 times speed-up and 4 times high integration capability without RC-delay increase
Keywords :
CMOS integrated circuits; application specific integrated circuits; integrated circuit design; integrated circuit manufacture; integrated circuit metallisation; optimisation; 0.2 micron; ASIC; CMOS device process; MPU; line-repeaters; long metal wires; manufacturable CMOS device; optimization strategy; scaling rule; seven-layer metal; thermal runaway; threshold voltage limitation; wiring channel density; CMOS process; CMOS technology; Circuit testing; Guidelines; Large scale integration; Leakage current; Packaging; Power dissipation; Threshold voltage; Wires;
Conference_Titel :
Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-4292-5
DOI :
10.1109/CICC.1998.694926
