DocumentCode :
2217152
Title :
Optimizing sequential verification by retiming transformations
Author :
Cabodi, Gianpiero ; Quer, Stefano ; Somenzi, Fabio
Author_Institution :
Politecnico di Torino
fYear :
2000
fDate :
2000
Firstpage :
601
Lastpage :
606
Keywords :
Boolean functions; Clocks; Computational efficiency; Data structures; Formal verification; Latches; Permission; Reachability analysis; Sequential circuits; State-space methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2000. Proceedings 2000
Print_ISBN :
1-58113-187-9
Type :
conf
DOI :
10.1109/DAC.2000.855382
Filename :
855382
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2217152
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