Title :
Modeling of single-transistor latch behavior in partially-depleted (PD) SOI CMOS devices using a concise SOI-SPICE model
Author :
Kuo, James B. ; Lin, Shih-Chia
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Abstract :
This paper presents modeling of single-transistor latch behavior in partially-depleted (PD) SOI CMOS devices using a concise SOI-SPICE BiCMOS model. As verified by the experimental data and MEDICI simulation results, the concise SOI-SPICE BiCMOS model predicts well the hysteresis and the latched conditions of PD SOI NMOS devices via monitoring VBE of the parasitic BJT.
Keywords :
MOSFET; SPICE; flip-flops; semiconductor device models; silicon-on-insulator; MEDICI simulation; NMOS device; SOI-SPICE BiCMOS model; hysteresis; parasitic BJT; partially-depleted SOI CMOS device; single-transistor latch; BiCMOS integrated circuits; CMOS technology; Hysteresis; Latches; MOS devices; SPICE; Semiconductor device modeling; Thin film circuits; Thin film devices; Very large scale integration;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on
Print_ISBN :
0-7803-6520-8
DOI :
10.1109/ICSICT.2001.982038
