Title :
A merged 2.5 V and 3.3 V 0.25-μm CMOS technology for ASICs
Author :
Kizilyalli, I.C. ; Huang, R. ; Hwang, D. ; Vaidya, H. ; Kane, B. ; Ashton, R. ; Kuehne, S. ; Deng, X. ; Twiford, M. ; Shuttleworth, D. ; Martin, E. ; Li, X. ; Thoma, J.
Author_Institution :
Bell Labs., Lucent Technol., Orlando, FL, USA
Abstract :
In this paper a merged 2.5 V and 3.3 V high performance 0.25 μm CMOS ASIC technology is presented. This technology features a 50 Å gate oxide, n+-polysilicon gate, and 4/5 levels of metal. An improvement of 1.45× in circuit performance and 3.7× in packing density is achieved over our previous generation 0.35 μm CMOS technology by device scaling and aggressive design rules. The nominal ring oscillator delay time is 38 ps
Keywords :
CMOS integrated circuits; application specific integrated circuits; integrated circuit technology; 0.25 micron; 2.5 V; 3.3 V; 50 A; ASICs; aggressive design rules; device scaling; merged 2.5/3.3 V CMOS technology; n+-polysilicon gate; Application specific integrated circuits; Birds; CMOS technology; Delay; Dielectrics; Implants; Integrated circuit technology; Isolation technology; Ring oscillators; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-4292-5
DOI :
10.1109/CICC.1998.694927
