DfT support for serial non-volatile sRAM´s

This paper gives an overview about the collaboration between test development and design of complex mixed signal devices such as nvSRAMs, with digital interface and control part; a huge analog part including oscillator, band gap, comparators, POR (power on reset) and BOR (brown out reset) circuitry; power supply monitoring, power control and charge pump; and volatile and non volatile memory arrays. Actually the final device is a trade-off between minimal chip size, design overhead and wafer sort and final test effort. Reliability is extremely important for non-volatile memories, therefore, it was useful to add special instructions and sub-circuits to support reliability testing as much as possible and to enable access to non-volatile information until end of life (EOL) of the device.