A high resolution, multi-path gated ring oscillator based Vernier Time-to-Digital Converter

The objective of this paper is novel circuit design and simulation for Vernier Time-to-Digital Converter (VTDC), that is using two multi-path Gated Ring Oscillator (GRO). An 11bit VTDC with 4ps effective resolution was designed and developed for a high performance All Digital Frequency Synthesizer (ADFS). The VTDC architecture combines digital standard cells accurate and arbiter circuits to make the time interval measurement, thus the VTDC is portable and scalable to other process technologies. The VTDC realized in 180nm CMOS and power consumes depending on the time difference between input edges; 1 to 11 mA from a 1.5 V supply.