DocumentCode
2217877
Title
A switch level fault simulation environment
Author
Krishnaswamy, V. ; Casas, J. ; Tetzlaff, T.
Author_Institution
Intel Corporation
fYear
2000
fDate
2000
Firstpage
780
Lastpage
785
Keywords
Algorithm design and analysis; Bridge circuits; Circuit faults; Circuit simulation; Databases; Delay; Logic devices; Switches; Switching circuits; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2000. Proceedings 2000
Print_ISBN
1-58113-187-9
Type
conf
DOI
10.1109/DAC.2000.855419
Filename
855419
Link To Document