DocumentCode :
2217920
Title :
A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications
Author :
Hanami, Atsuo ; Scotzniovsky, Stefan ; Ishihara, Kazuya ; Matsumura, Tetsuya ; Takeuchi, Shin-ichi ; Ohkuma, T. Haruyuki ; Nishigaki, Koji ; Suzuki, Hirokazu ; Kazayama, Masahiro ; Yoshida, Toyohiko ; Tsuchihashi, Koji
Author_Institution :
Syst. LSI Div., Mitsubishi Electr. Corp., Hyogo, Japan
fYear :
1998
fDate :
11-14 May 1998
Firstpage :
169
Lastpage :
172
Abstract :
A wide range motion estimation with exhaustive search is the best approach for high quality encoding applications. To perform the required computational power, a 165 GOPS (giga operations per second) exhaustive motion estimation processor ME3 has been developed. The ME3 is powerful enough to realize a range of -64/+63 pixels horizontally and -32/+31 pixels vertically with a single chip. A dual-array architecture supports not only high calculation power but also luminance and chrominance based search to increase picture quality. Also, the ME3 outputs extra vectors as candidates to enhance the picture quality. Using a multi-chip configuration, the exhaustive search range can be easily expanded to meet the requirements of MP@HL encoder. It is implemented using 0.35 μm CMOS technology and contains 1.9 million transistors in an area of 8.5×8.5 mm2
Keywords :
CMOS digital integrated circuits; VLSI; digital signal processing chips; motion estimation; parallel architectures; video coding; 0.35 micron; CMOS technology; ME3 processor; adaptive dual-array architecture; chrominance based search; exhaustive search; high quality video-encoding applications; luminance based search; motion estimation processor; multi-chip configuration; picture quality enhancement; Adaptive arrays; CMOS technology; Costs; Encoding; Information technology; Laboratories; Large scale integration; Motion estimation; Research and development; Search methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-4292-5
Type :
conf
DOI :
10.1109/CICC.1998.694929
Filename :
694929
Link To Document :
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