Title :
Power minimization using control generated clocks
Author :
Rao, Mayuri Sathyanarayana ; Nandy, S.K.
Author_Institution :
Indian Institute of Science
Keywords :
Circuit synthesis; Circuit testing; Clocks; Driver circuits; Minimization; Power dissipation; Power generation; Registers; Sequential circuits; Timing;
Conference_Titel :
Design Automation Conference, 2000. Proceedings 2000
Print_ISBN :
1-58113-187-9
DOI :
10.1109/DAC.2000.855422
