Logic framework for high-speed serial links in SiGe BiCMOS

This paper presents a logic framework for the use in multi-Gbit/s serial communications, allowing a rapid design of common building blocks such as multiplexers or phase detectors. The framework consists of logic gates and interconnect stages using bandwidth-enhanced static emitter coupled logic (ECL) topology. Especially at high data rates, the influence of on-chip interconnects cannot be neglected and is therefore addressed. The functionality of the framework was verified by an integrated phase detector for clock and data recovery (CDR) systems in a 0.25 μm SiGe HBT BiCMOS technology, showing operability up to 50 Gbit/s.