Issues in partitioning integrated circuits for MCM-D/flip-chip technology

Author

Banerjia, Sanjeev ; Glaser, Alan ; Harvatis, Christoforos ; Lipa, Steve ; Pomerleau, Real ; Schaffer, Toby ; Stanaski, Andrew ; Tekmen, Yusuf ; Bilbro, Grif ; Franzon, Paul

Author_Institution

Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA

fYear

1996

fDate

6-7 Feb 1996

Firstpage

154

Lastpage

159

Abstract

In order to successfully partition a high performance large monolithic chip onto MCM-D/flip-chip-solder-bump technology, a number of key issues must be addressed. These include the following: (1) Partitioning a single clock-cycle path across the chip boundary within using; (2) Ability to use off-the-shelf memories; (3) Using the MCM for power, ground, and clock distribution; and (4) Managing test costs. This paper presents a discussion on these issues, using a CPU as an example, and speculates on some interesting possibilities arising from partitioning

Keywords

clocks; flip-chip devices; integrated circuit packaging; logic partitioning; microprocessor chips; multichip modules; CPU chip; IC partitioning; MCM-D/flip-chip technology; chip boundary; clock distribution; ground distribution; microprocessor chips; power distribution; single clock-cycle path; test costs; Central Processing Unit; Clocks; Costs; Energy management; Integrated circuit technology; Logic; Memory management; Random access memory; Testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Multi-Chip Module Conference, 1996. MCMC-96, Proceedings., 1996 IEEE

Conference_Location

Santa Cruz, CA

Print_ISBN

0-8186-7286-2

Type

conf

DOI

10.1109/MCMC.1996.510787

Filename

510787