Design of a fast, easily testable ALU

Author

Blanton, R.D. ; Hayes, John P.

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

1996

fDate

28 Apr-1 May 1996

Firstpage

9

Lastpage

16

Abstract

The design and implementation of a fast, easily testable arithmetic-logic unit (ALU) is described. It is built around an adder design which is level-testable (L-testable), implying that the number of test patterns required to detect all functional faults in modules grows logarithmically with the size of the ALU. L-testability is achieved by exploiting some inherent properties of carry-lookahead addition. The resulting ALU design requires only two extra inputs, regardless of the size of the ALU. For an 8-bit implementation that has little impact on performance, the area overhead is shown to be less than 9%

Keywords

adders; automatic testing; carry logic; digital arithmetic; fault diagnosis; integrated circuit design; integrated circuit testing; logic arrays; logic testing; 8 bit; ALU; L-testable design; adder design; area overhead; arithmetic-logic unit; carry-lookahead addition; functional faults; level-testable; test patterns; Adders; Bismuth; Costs; Delay; Hardware; Logic arrays; Logic design; Logic testing; Multiplexing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1996., Proceedings of 14th

Conference_Location

Princeton, NJ

ISSN

1093-0167

Print_ISBN

0-8186-7304-4

Type

conf

DOI

10.1109/VTEST.1996.510829

Filename

510829