A self-driven test structure for pseudorandom testing of non-scan sequential circuits

Author

Muradali, Fidel ; Rajski, Janusz

Author_Institution

Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada

fYear

1996

fDate

28 Apr-1 May 1996

Firstpage

17

Lastpage

25

Abstract

Introduced is a self-driven test point structure which permits at-speed, on-chip, non-scan, sequential testing using parallel pseudorandom test patterns applied only to the primary inputs of the circuit under test. The test network is unique in that aside from a test mode flag, all I/O signals needed for test system operation are tapped from within the circuit itself. High single stuck-at fault coverage is achieved for a number of ISCAS-89 benchmarks

Keywords

automatic testing; built-in self test; design for testability; integrated circuit testing; logic testing; sequential circuits; BIST; ISCAS-89 benchmarks; circuit under test; nonscan sequential circuits; parallel pseudorandom test patterns; primary inputs; self-driven test structure; stuck-at fault coverage; test mode flag; test point structure; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Degradation; Design for testability; Logic testing; Sequential analysis; Sequential circuits; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1996., Proceedings of 14th

Conference_Location

Princeton, NJ

ISSN

1093-0167

Print_ISBN

0-8186-7304-4

Type

conf

DOI

10.1109/VTEST.1996.510830

Filename

510830