Tradeoff between complexity and memory size in the 3GPP enhanced aacPlus decoder: Speed-conscious and memory-conscious decoders on a 16-bit fixed-point DSP

Author

Shimada, Osamu ; Nomura, Toshiyuki ; Sugiyama, Akihiko ; Serizawa, Masahiro

Author_Institution

Media & Inf. Res. Labs., NEC Corp., Kawasaki, Japan

fYear

2006

fDate

4-8 Sept. 2006

Firstpage

1

Lastpage

5

Abstract

This paper investigates tradeoff between complexity and memory size in the 3GPP enhanced aacPlus decoder based on 16-bit fixed-point DSP implementation. In order to investigate this tradeoff, the speed- and the-memory conscious decoders are implemented. The maximum number of operations for the implemented speed-conscious decoder is 29.3 million cycles per second (MCPS) for a 32 kb/s bitstream. The maximum number of operations for the memory-conscious decoder, where 70% of the data are allocated to an external memory area, increases by 5.7 MCPS (19%) for the bitstream. The investigation of this tradeoff provides an actual relationship between the computational complexity and the internal memory size of the 3GPP enhanced aacPlus decoder. The implemented decoders enable music download and streaming services on next-generation mobile terminals.

Keywords

codecs; computational complexity; digital signal processing chips; mobile radio; next generation networks; 3GPP enhanced aacPlus decoder; DSP; bit rate 32 kbit/s; computational complexity; memory-conscious decoders; music download; next-generation mobile terminals; speed-conscious decoders; streaming services; word length 16 bit; Abstracts; Audio coding; Complexity theory; Decoding; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Conference, 2006 14th European

Conference_Location

Florence

ISSN

2219-5491

Type

conf

Filename

7071365