DocumentCode
2219315
Title
Standard and ROM-based synthesis of FSMs with control flow checking capabilities
Author
Wendling, X. ; Rochet, R. ; Leveugle, R.
Author_Institution
Inst. Nat. Polytech. de Grenoble, France
fYear
1996
fDate
28 Apr-1 May 1996
Firstpage
81
Lastpage
86
Abstract
This paper deals with the detection of sequencing errors in finite state machines. Several control-flow checking methods, implemented in an automatic synthesis tool, are presented. The contribution of this paper lies in that these methods are introduced in the ROM-based architecture, and compared to equivalent methods available in the standard synthesis flow
Keywords
automatic testing; error detection; finite state machines; integrated circuit design; integrated circuit testing; read-only storage; FSM; ROM architecture; automatic synthesis; control flow checking; finite state machine; sequencing error detection; Delay; Law; Logic; Monitoring; Polynomials; Runtime; Shift registers; Sufficient conditions; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1996., Proceedings of 14th
Conference_Location
Princeton, NJ
ISSN
1093-0167
Print_ISBN
0-8186-7304-4
Type
conf
DOI
10.1109/VTEST.1996.510839
Filename
510839
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