DocumentCode
2219400
Title
Development of test programs in a virtual test environment
Author
Miegler, M. ; Wolz, W.
Author_Institution
Inst. of Comput.-Aided Circuit Design, Erlangen-Nurnberg Univ., Germany
fYear
1996
fDate
28 Apr-1 May 1996
Firstpage
99
Lastpage
103
Abstract
An environment for the efficient development of quality-assured mixed-signal test programs is introduced. The new approach provides links between design and test engineers based on a standard test description language VTML (Virtual Test Modelling Language). The language provides standardized description models for test system resources which can be mapped as well to equivalent simulation models as to real world test system hardware. Methods are provided to check the data consistency of test programs and to validate test program behavior using simulation models
Keywords
VLSI; automatic test software; circuit CAD; design for testability; integrated circuit design; integrated circuit testing; VTML; Virtual Test Modelling Language; equivalent simulation models; quality-assured mixed-signal test programs; standard test description language; standardized description models; test programs development; test system resources; virtual test environment; Automatic testing; Circuit testing; Computational modeling; Computer aided engineering; Design engineering; Hardware; Instruments; Integrated circuit testing; System testing; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1996., Proceedings of 14th
Conference_Location
Princeton, NJ
ISSN
1093-0167
Print_ISBN
0-8186-7304-4
Type
conf
DOI
10.1109/VTEST.1996.510842
Filename
510842
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