Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems

In this paper it is shown how a self-checking checker can be designed to monitor systems with very few encoded outputs which are code words of an arbitrary separable error detection code. The checker is completely tested in normal operation mode, independent of the number of code words which are to be monitored. If an error has been indicated in normal operation mode the erroneous component of the system can be identified in test mode by the same hardware. A linear feedback shift register (LFSR) is included between the information bits of the outputs of the monitored systems and the inputs of the check-bit generator. A corrector (Cor) adjusts the check bits of the monitored system. The general systematic design method given in this paper is applied to parity codes, duplication codes, arithmetic codes and Berger codes. The approach is useful for the design of ultra-reliable fault-tolerant systems, especially for monitoring systems with very few outputs in normal operation mode