Title :
A CAD-based approach to failure diagnosis of CMOS LSI´s using abnormal Iddq
Author_Institution :
NEC Corp., Kawasaki, Japan
fDate :
28 Apr-1 May 1996
Abstract :
A CAD-based failure diagnosis technology for CMOS LSI´s using abnormal Iddq has been developed to indicate the presence of physical damage in a circuit. By using set operations to compare the portions of an LSI that exhibit abnormal Iddq with the portions of an LSI that exhibit normal Iddq, this new method can progressively reduce the set of possible faulty blocks to localize a defect. To easily perform failure diagnosis, the expected input combination of each block, determined for simulation dump list of expected internal node value, is applied. This paper describes the abnormal Iddq phenomenon and the method of failure point localization using abnormal Iddq test patterns. The ISCAS´85 C17 benchmark was applied to verify this new diagnostic technique
Keywords :
CMOS logic circuits; automatic testing; circuit CAD; fault diagnosis; integrated circuit testing; large scale integration; logic testing; CAD-based failure diagnosis technology; CMOS LSI; Iddq test patterns; abnormal Iddq phenomenon; failure point localization; faulty blocks; physical damage detection; CMOS technology; Circuit faults; Degradation; Failure analysis; Fault diagnosis; Large scale integration; Leakage current; Life testing; Logic testing; Temperature;
Conference_Titel :
VLSI Test Symposium, 1996., Proceedings of 14th
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7304-4
DOI :
10.1109/VTEST.1996.510856
