• DocumentCode
    2219825
  • Title

    FPGA architecture for object segmentation in real time

  • Author

    Parente de Oliveira, Jozias ; Printes, Andre Luiz ; Silverio Freire, Raimundo Carlos ; Melcher, Elmar Uwe Kurt ; De Souza Silva, Ivan Sebastiao

  • Author_Institution
    Genius Inst. of Technol., Manaus, Brazil
  • fYear
    2006
  • fDate
    4-8 Sept. 2006
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Object segmentation from a video sequence is a function necessary for many applications of artificial vision systems such as: video surveillance, traffic monitoring, detection and tracking for video teleconferencing, video editing, etc. In this paper, we present an architecture for object segmentation, taking advantage of the data and logical parallel opportunities offered by a field programmable gate array (FPGA) architecture. At a clock rate of 40 MHz, the architecture can process 30 frames per second, where the image resolution is 240 × 120..
  • Keywords
    field programmable gate arrays; image segmentation; image sequences; logic design; FPGA architecture; artificial vision systems; field programmable gate array; frequency 40 MHz; object segmentation; traffic monitoring; video editing; video sequence; video surveillance; video teleconferencing; Abstracts; Europe; Field programmable gate arrays; Image resolution; Image segmentation; Random access memory; Streaming media;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing Conference, 2006 14th European
  • Conference_Location
    Florence
  • ISSN
    2219-5491
  • Type

    conf

  • Filename
    7071394