Design of a fault tolerant 100 Gbits solid-state mass memory for satellites

Author

Kluth, M.P. ; Simon, F. ; Le Gall, J.-Y. ; Müller, E.

Author_Institution

Autom. & Intelligent Syst. Unit., Alcatel Alsthom Recherche, Marcoussis, France

fYear

1996

fDate

28 Apr-1 May 1996

Firstpage

281

Lastpage

286

Abstract

This paper summarizes the studies conducted by Alcatel Espace and Alcatel Alsthom Recherche to design a new generation of fault tolerant 100 Gbits mass memories for satellites, based on VLSI components. In the context of space applications, stringent dependability constraints have to be met and fault tolerance is a design objective. To reach this tolerance mechanisms including error detection and tests are needed

Keywords

VLSI; aerospace computing; error detection; fault tolerant computing; integrated circuit testing; semiconductor storage; special purpose computers; 100 Gbit; VLSI components; error detection; fault tolerant solid-state mass memory; satellite applications; space applications; testing; Automation; Computer interfaces; Fault tolerance; Fault tolerant systems; Intelligent systems; Memory management; Satellites; Solid state circuits; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1996., Proceedings of 14th

Conference_Location

Princeton, NJ

ISSN

1093-0167

Print_ISBN

0-8186-7304-4

Type

conf

DOI

10.1109/VTEST.1996.510869

Filename

510869

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2220032