Title :
Low power adder with adaptive supply voltage
Author :
Suzuki, Hiroaki ; Jeong, Woopyo ; Roy, Kaushik
Author_Institution :
Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a low power adder, which adoptively selects supply voltages based on the input vector patterns. We prototyped a 32-bit Ripple Carry Adder and analyzed the power consumption and performance in details. Results show 29% improvement in power consumption over a conventional ripple carry adder with comparable performance.
Keywords :
CMOS integrated circuits; VLSI; adders; carry logic; power consumption; adaptive supply voltage; low power VLSI; ripple carry adder; Adders; CMOS technology; Circuits; Clocks; Degradation; Design methodology; Energy consumption; Propagation delay; Very large scale integration; Voltage;
Conference_Titel :
Computer Design, 2003. Proceedings. 21st International Conference on
Print_ISBN :
0-7695-2025-1
DOI :
10.1109/ICCD.2003.1240880
