On completely robust path delay fault testable realization of logic functions

Author

Vardanian, V.A.

Author_Institution

Inst. of Inf. & Autom. Problems, Acad. of Sci., Yerevan, Armenia

fYear

1996

fDate

28 Apr-1 May 1996

Firstpage

302

Lastpage

307

Abstract

A large class of Boolean functions, as well as almost all symmetric Boolean functions, are shown to have no two-level completely robust path-delay-fault testable (RPDFT) realization by combinational circuits. Exact and asymptotic formulae are derived for the number of symmetric Boolean functions which have two-level completely RPDFT realization. To achieve completely RPDFT realization, a notion of RPDFT-extension is proposed for logic functions which have no two-level completely RPDFT realization. Algorithms are devised for the design of RPDFT-extensions with at most 2 extra input variables

Keywords

Boolean functions; VLSI; combinational circuits; delays; fault diagnosis; integrated circuit testing; logic testing; multivalued logic circuits; Boolean functions; RPDFT-extension; VLSI; combinational circuits; input variables; robust path delay fault testable realization; symmetric functions; two-level completely RPDFT realization; Algorithm design and analysis; Boolean functions; Circuit faults; Circuit testing; Combinational circuits; Delay; Input variables; Logic functions; Logic testing; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1996., Proceedings of 14th

Conference_Location

Princeton, NJ

ISSN

1093-0167

Print_ISBN

0-8186-7304-4

Type

conf

DOI

10.1109/VTEST.1996.510872

Filename

510872