Title :
Quantitative analysis of very-low-voltage testing
Author :
Chang, Jonathan T -Y ; McCluskey, Edward J.
Author_Institution :
Center for Reliable Comput., Stanford Univ., CA, USA
fDate :
28 Apr-1 May 1996
Abstract :
Some weak static CMOS chips can be detected by testing them with a very low supply voltage-between 2 and 2.5 times the threshold voltage V t of the transistors. A weak chip is one that contains a flaw-an imperfection that does not interfere with correct operation at rated conditions but which may cause intermittent or early-life failures. This paper considers several types of flaws and derives the test conditions for them. It also proposes two approaches for determining the appropriate test speed for very-low-voltage testing
Keywords :
CMOS integrated circuits; VLSI; failure analysis; integrated circuit noise; integrated circuit testing; VLSI; early-life failures; quantitative analysis; rated conditions; static CMOS chips; supply voltage; test conditions; test speed; threshold voltage; very-low-voltage testing; CMOS digital integrated circuits; CMOS integrated circuits; CMOS process; CMOS technology; Circuit simulation; Circuit testing; Delay; Integrated circuit noise; MOSFETs; Threshold voltage;
Conference_Titel :
VLSI Test Symposium, 1996., Proceedings of 14th
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7304-4
DOI :
10.1109/VTEST.1996.510876
