Bridging fault coverage improvement by power supply control

Author

Renovell, M. ; Huc, P. ; Bertrand, Y.

Author_Institution

Lab. d´´Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France

fYear

1996

fDate

28 Apr-1 May 1996

Firstpage

338

Lastpage

343

Abstract

This paper analyses the impact of the power supply voltage on the logical behavior of resistive Bridging Fault. It is theoretically demonstrated that the interval of resistance corresponding to the appearance of a faulty value exponentially increases when the power supply decreases. Using the Parametric Model specifically developed for resistive bridging faults, results of parametric bridging faults simulations on benchmark circuits clearly show an improvement of about 40% when a lower-than-normal power supply is used. Moreover this bridging fault coverage improvement technique doesn´t need any additional effort such as Design for Testability or specific Test Pattern Generation

Keywords

VLSI; automatic testing; fault diagnosis; integrated circuit testing; logic testing; VLSI; benchmark circuits; bridging fault coverage; faulty value; logic circuits; parametric model; power supply control; resistance interval; Circuit faults; Circuit simulation; Fault detection; Logic; Parametric statistics; Power supplies; Test pattern generators; Testing; Threshold voltage; Voting;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1996., Proceedings of 14th

Conference_Location

Princeton, NJ

ISSN

1093-0167

Print_ISBN

0-8186-7304-4

Type

conf

DOI

10.1109/VTEST.1996.510877

Filename

510877