DocumentCode :
2220255
Title :
Efficient synthesis of networks on chip
Author :
Pinto, Alessandro ; Carloni, Luca P. ; Sangiovanni-Vincentelli, Alberto L.
Author_Institution :
EECS Dept., California Univ., Berkeley, CA, USA
fYear :
2003
fDate :
13-15 Oct. 2003
Firstpage :
146
Lastpage :
150
Abstract :
We propose an efficient heuristic for the constraint-driven communication synthesis (CDCS) of on-chip communication networks. The complexity of the synthesis problems comes from the number of constraints that have to be considered. We propose to cluster constraints to reduce the number that needs to be considered by the optimization algorithm. Then a quadratic programming approach is used to solve the communication synthesis problem with the clustered constraints. We provide an analytical model that justifies our choice of the clustering cost function and we discuss a set of experiments showing the effectiveness of the overall approach with respect to the exact algorithm.
Keywords :
communication complexity; constraint handling; network synthesis; quadratic programming; system-on-chip; telecommunication networks; CDCS; analytical model; cluster constraint; constraint driven communication synthesis; on-chip communication network; optimization algorithm; quadratic programming; Clustering algorithms; Communication networks; Constraint optimization; Cost function; Libraries; Network synthesis; Network-on-a-chip; Quadratic programming; Scalability; Topology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design, 2003. Proceedings. 21st International Conference on
ISSN :
1063-6404
Print_ISBN :
0-7695-2025-1
Type :
conf
DOI :
10.1109/ICCD.2003.1240887
Filename :
1240887
Link To Document :
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