Design and performance of CMOS TSPC cells for high speed pseudo random testing

Author

Soufi, Mohamed ; Rochon, Steve ; Savaria, Yvon ; Kaminska, Bozena

Author_Institution

Ecole Polytech. de Montreal, Que., Canada

fYear

1996

fDate

28 Apr-1 May 1996

Firstpage

368

Lastpage

373

Abstract

In this paper the problem of testing high speed CMOS circuits is considered. A test methodology based on a Built-in Self-Test scheme adapted to TSPC circuits is proposed. We show through HSpice simulations on netlists extracted from layout that this scheme can operate at more than 580 MHz. Moreover, an efficient solution to the problem of redesigning an easily testable functionally equivalent logic block to eliminate hard to test and untestable faults in TSPC circuits is introduced

Keywords

CMOS logic circuits; SPICE; built-in self test; cellular arrays; circuit analysis computing; circuit layout CAD; clocks; integrated circuit layout; integrated circuit testing; logic CAD; logic testing; CMOS TSPC cells; HSpice simulations; built-in self-test scheme; functionally equivalent logic block; high speed pseudo random testing; layout; netlists; test methodology; true single phase clocking; untestable faults; Automatic testing; Built-in self-test; CMOS technology; Circuit simulation; Circuit testing; Clocks; Design methodology; Latches; Logic testing; Pipelines;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1996., Proceedings of 14th

Conference_Location

Princeton, NJ

ISSN

1093-0167

Print_ISBN

0-8186-7304-4

Type

conf

DOI

10.1109/VTEST.1996.510880

Filename

510880