Title :
Physical design of the "2.5D" stacked system
Author :
Deng, Yangdong ; Maly, Wojciech
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
Excessive on-chip wire length and fast increasing fabrication cost have been the main factors impairing the effectiveness of monolithic system-on-chip. We investigate a die stacking based system integration strategy (2.5D system integration) to address these problems. The new scheme is design-tools-enabled rather than technology-driven. We developed a layout design framework, which is able to floorplan, place and route a VLSI design into stacked chips. Our results show that this new scheme has a potential to outperform its monolithic equivalent.
Keywords :
VLSI; circuit layout CAD; integrated circuit interconnections; integrated circuit layout; system-on-chip; 2.5D stacked system design; VLSI design; circuit layout design; die stacking; floorplanning; monolithic system-on-chip; system integration strategy; Costs; Delay; Fabrication; Integrated circuit interconnections; Logic design; Random access memory; Stacking; System-on-a-chip; Timing; Wire;
Conference_Titel :
Computer Design, 2003. Proceedings. 21st International Conference on
Print_ISBN :
0-7695-2025-1
DOI :
10.1109/ICCD.2003.1240897
