Hardware-only compression of underutilized address buses: design and performance, power, and cost analysis

Minimizing the area/cost and power consumption of communication components (address, instruction, and data buses and associated hardware like I/O pins, pads, and buffers) is becoming important in modern microprocessors. Currently, utilization of buses is not taken into account during design of many bus systems. This may lead to underutilization of many buses during actual operation. We propose a scheme that exploits the underutilization of address buses to result in a cost-effective and energy-efficient bus system design. This is accomplished by using buses of narrow width, new encoding schemes for narrow buses, and with design of hardware that result in only a minimal impact on performance and power consumption. We show the efficacy of our schemes using simulations on a validated Alpha 21264 model for SimpleScalar and using physical address traces from 14 SPEC CPU2000 benchmarks.