Hardware implementation of a neural network based path planning algorithm by using the VHDL

Author

Chan, Ricky H T ; Tam, Peter K S ; Kwok, D.P. ; Cheung, Philip W M

Author_Institution

Dept. of Electron. Eng., Hong Kong Polytech., Hung Hom, Hong Kong

fYear

1993

fDate

15-19 Nov 1993

Firstpage

310

Abstract

This paper presents a new approach for designing a neural network based path planning algorithm in an integrated circuit by using the VHDL. VHDL is the name of the IEEE 1076 hardware description language standard for very high speed digital circuit design. The structure of the VHDL provides a convenient construct for the implementation of neural network into electronic hardware. In addition, with VHDL analyzer and logic synthesis software, hardware prototypes can be implemented in ASIC, especially field programmable gate array, automatically

Keywords

application specific integrated circuits; circuit CAD; logic CAD; logic arrays; mobile robots; neural chips; path planning; specification languages; ASIC; FPGA; IEEE 1076 hardware description language standard; VHDL analyzer; field programmable gate array; logic synthesis software; neural network based path planning algorithm; very high speed digital circuit design; Algorithm design and analysis; Automatic logic units; Digital circuits; Hardware design languages; Integrated circuit synthesis; Network synthesis; Neural network hardware; Neural networks; Path planning; Programmable logic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Electronics, Control, and Instrumentation, 1993. Proceedings of the IECON '93., International Conference on

Conference_Location

Maui, HI

Print_ISBN

0-7803-0891-3

Type

conf

DOI

10.1109/IECON.1993.339061

Filename

339061