• DocumentCode
    2220607
  • Title

    Testing trees for multiple faults

  • Author

    Vergis, Anastasios ; Tobon, Carlos

  • Author_Institution
    Dept. of Comput. Eng., Patras Univ., Greece
  • fYear
    1996
  • fDate
    28 Apr-1 May 1996
  • Firstpage
    444
  • Lastpage
    449
  • Abstract
    A “well behaving” property is defined for each line (in general a bundle of wires) connecting two combinational logic cells. This property can be easily taken into account in the design process of the circuit. It is shown that all tree-structured circuits of combinational logic cells are easily testable for multiple faults if each line is “well behaving”. The size of the test set increases only linearly as the number of cells increases. It is also shown that if no line is well-behaving then only the trivial (exhaustive) test set exists for the circuit, which increases exponentially as the number of cells increases. If there are well-behaving as well as non-well-behaving lines in the circuit, then the size of the test set increases exponentially with the sizes of the non-well-behaving subtrees and linearly with the number of such subtrees
  • Keywords
    VLSI; combinational circuits; design for testability; integrated circuit testing; integrated logic circuits; logic design; logic testing; combinational logic cells; multiple faults; test set size; testing trees; tree-structured circuits; Circuit faults; Circuit testing; Electrical fault detection; Multivalued logic; Tree data structures; Very large scale integration; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1996., Proceedings of 14th
  • Conference_Location
    Princeton, NJ
  • ISSN
    1093-0167
  • Print_ISBN
    0-8186-7304-4
  • Type

    conf

  • DOI
    10.1109/VTEST.1996.510891
  • Filename
    510891