Synthesis of optimal high performance DSP applications with emerging CAD technologies

In this paper we present a case study of customized processor architecture design, at the RTL level, for high performance digital signal processing applications, using specialized CAD tools. The algorithm in this model design is the LD-CELP, low delay code excited linear prediction, for the coding and decoding of speech at 16 Kbit/sec. The LD-CELP algorithm achieves a 1:4 reduction in bit rate over linear PCM, at the cost of significant computational complexity. We illustrate the way in which the tools used in the design are unconventional and have led to a design discipline equally so. Furthermore, we demonstrate how we capitalized on the design discipline in order to cut design cycle time significantly and how we managed the design complexity of the implementation of the algorithm