A design of high-speed and low-consume parallel grouping RS code and simulation

RS code is a linear error correction codes with better error correction capability, is widely used in different kinds of occasions for communications or data storage. But for its high difficulty of coding and decoding algorithm and low throughput, optimization RS algorithm is always studied as one of the focus in the error-correction field. A new coding method, parallel coding and decoding data into groups in lower step finite field for avoiding complex matrix iteration and Chien search computation, is proposed in this paper. It is proved that the coding and decoding throughput of the parallel grouping RS coder is increased and the hardware complexity is reduced with changeless error-correction capability from the simulation results using ModelSim SE 6.0 and synthetic results using ISE 9.11σ.