DocumentCode :
2221616
Title :
SAT-based algorithms for logic minimization
Author :
Sapra, Samir ; Theobald, Michael ; Clarke, Edmund
Author_Institution :
Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear :
2003
fDate :
13-15 Oct. 2003
Firstpage :
510
Lastpage :
517
Abstract :
We introduce a new method for two-level logic minimization. Unlike previous approaches, the new method uses a SAT solver as an underlying engine. While the overall minimization strategy of the new method is based on the operators as defined in ESPRESSO-II, our SAT-based implementation is significantly different. The new minimizer SAT-ESPRESSO was found to perform 5-20 times faster than ESPRESSO-II and 3-5 times faster than BOOM on a set of large examples.
Keywords :
computability; computational complexity; minimisation of switching nets; BOOM; ESPRESSO-II; SAT solver; SAT-ESPRESSO; SAT-based algorithm; logic minimization; Circuit synthesis; Circuit testing; Contracts; Engines; Logic circuits; Logic design; Logic functions; Logic gates; Logic testing; Minimization methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design, 2003. Proceedings. 21st International Conference on
ISSN :
1063-6404
Print_ISBN :
0-7695-2025-1
Type :
conf
DOI :
10.1109/ICCD.2003.1240948
Filename :
1240948
Link To Document :
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