Optimization of advanced bipolar ECL gates through statistical circuit simulation

Emitter-coupled logic (ECL) configurations that can be used in high-density gate arrays have been studied for a wide range of input conditions. CAD methodology which requires minimal user interaction is used. First, a general circuit schematic is created, allowing inputs to be varied. The basic schematic also incorporates estimates of layout-related parasitics. All the generic gates are tied together in the form of a ring oscillator. An internally written program then links the circuit configuration with other forced conditions such as voltage and temperature to the circuit simulator (MSPICE) with minimal designer interaction. Variations on all input variables are made through a Box-Benhken design so as to substantially reduce the number of simulations required in order to fit an approximating multi-dimensional quadratic output response surface to the inputs. The output of each circuit simulation (i.e. delay, power consumption, etc.) is automatically extracted and saved along with all its corresponding inputs. In the present experiment, a seven-factor Box-Benhken design was chosen using gate current, follower current, fan out, metal interconnect loading, voltage swing, and device size (Ae) as the input factors. The experiment required a total of 57 simulations, which were all run in batch mode. The output was analyzed using the statistical package SAS. For a given output (i.e. gate delay) an approximating quadratic polynomial, in terms of the seven inputs, is fit by the method of least squares. A ranking of the most important input variables as well as the correlation between two or more inputs can be obtained with this method