Title :
Auto-synthesis of series-gated emitter-coupled logic
Author :
Choy, Chiu-sing Oliver
Author_Institution :
Dept. of Electron., Chinese Univ. of Hong Kong, Shatin, Hong Kong
Abstract :
A systematic technique for synthesizing series-gated emitter-coupled logic (ECL) for any logic function is described. The technique is applied in an auto-synthesis program whereby multilevel ECL circuit schematics are generated automatically from Boolean equation or truth table input. The resulting circuit uses a minimum number of transistors. The series gating method, minimization technique, and autosynthesis program are described
Keywords :
bipolar integrated circuits; emitter-coupled logic; integrated logic circuits; logic CAD; Boolean equation; ECL; any logic function; auto-synthesis program; autosynthesis program; minimization technique; minimum number of transistors; multilevel ECL circuit schematics; series gating method; series-gated emitter-coupled logic; systematic technique; truth table input; Circuit synthesis; Inverters; Libraries; Logic circuits; Logic devices; Logic functions; Logic gates; Minimization; Stacking; Voltage;
Conference_Titel :
Bipolar Circuits and Technology Meeting, 1989., Proceedings of the 1989
Conference_Location :
Minneapolis, MN
DOI :
10.1109/BIPOL.1989.69496
