Title :
Computational field programmable architecture
Author :
Kaviani, Alireza ; Vranesic, Daniel ; Brown, Stephen
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Abstract :
This paper introduces a new field-programmable architecture that is targeted at compute-intensive applications. These applications are important because of their use in the expanding multi-media markets in signal and data processing. We explain the design methodology, layout and implementation of the new architecture. A synthesis method has also been developed with which we have mapped several circuits to the new architecture. In this paper, we show that the invented architecture is more area-efficient than traditional FPGAs by a factor of more than 2.5 times
Keywords :
CMOS logic circuits; circuit CAD; field programmable gate arrays; high level synthesis; integrated circuit layout; network routing; FPGA; area-efficient architecture; computational field programmable architecture; compute-intensive applications; design methodology; layout; synthesis method; Adders; Application software; Computer applications; Computer architecture; Field programmable gate arrays; Integrated circuit interconnections; Logic circuits; Logic devices; Signal processing; Table lookup;
Conference_Titel :
Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-4292-5
DOI :
10.1109/CICC.1998.694976
