Custom Instruction Generation with High-Level Synthesis

This paper presents a novel approach for automatic custom instruction set generation with high-level synthesis techniques. Unlike previous approaches which generate a single custom instruction from each subgraph, the proposed approach generates a sequence of multiple custom instructions from each subgraph. Because of this feature, the proposed approach can not only generate custom instructions from multiple inputs multiple outputs (MIMO) subgraphs but also enables resource sharing among custom instructions. The technique is widely applicable to extensible processors with limited numbers of operands per instruction, such as RISCs, since it requires minimal changes in the architecture and instruction encoding of the processors. Experimental results show that proposed approach can generate custom instructions with average speedups of 20.5% and significant area reduction.