Title :
A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability
Author :
Reese, Dirk ; Chun, Eric ; Cheung, Sammy ; Lau, Edmond ; Chu, Michael ; Liang, Minchang ; Van Tran, Nghia ; Vest, Brad ; Smolen, Richard ; Minchang Liang ; Sekariapuram, Seshan ; Nouban, Behzad ; Wong, Myron ; Costello, John ; Turner, John
Author_Institution :
Altera Corp., San Jose, CA, USA
Abstract :
The methods and circuits used in the design of a high density, high performance, power efficient, complex PLD are discussed. The EPM9560A is the first member of the third generation MAX 9000 family. Developed on a 0.5 μm triple layer metal process, significant improvements in die size, performance, and power have been achieved over the previous generations. Circuit enhancements and design methodologies resulting in better performance are discussed. Analysis methods used in the design of a 560 macrocell PLD with a die size of 99.9 Kmil2 and a propagation delay under 7 ns are also discussed
Keywords :
CMOS logic circuits; EPROM; PLD programming; integrated circuit design; logic design; programmable logic arrays; 0.5 micron; 3.3 to 5 V; 6.9 ns; CMOS PLD; EEPROM array; EPM9560A; complex PLD; design methodologies; high density CPLD; in system programmability; macrocell; power efficient PLD; third generation MAX 9000 family; triple layer metal process; Delay; Design methodology; Driver circuits; Drives; EPROM; Feeds; Logic arrays; Macrocell networks; Power generation; Technological innovation;
Conference_Titel :
Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-4292-5
DOI :
10.1109/CICC.1998.694977
