DocumentCode :
2223386
Title :
A DRAM module generator with an expandable cell array scheme
Author :
Takeuchi, Hideki ; Yabe, Tomoaki ; Miyano, Shinji ; Hojo, Takehiko ; Enkaku, Motohiro ; Yamada, Masaaki ; Murakata, Masami
Author_Institution :
Semicond. DA & Test Eng. Center, Toshiba Corp., Kawasaki, Japan
fYear :
1998
fDate :
11-14 May 1998
Firstpage :
287
Lastpage :
290
Abstract :
This paper describes a DRAM module generator (DRAMGen) with an expandable cell array scheme. DRAMGen uses a modularization scheme. This expandable cell array scheme uses the cell array segment as the unit of increment and applies shared sense-amplifier scheme. This scheme reduces the area penalty to less than five percent and has little performance penalty. Using a 0.35 μm process technology, a series of DRAM macros with flexible bank, row, column, and I/O-bit configurations consequently produce 2112 derivatives. The module generator has successfully generated a number of macros, taking five seconds for each macro, including a 32 Mb macro with a 150 MHz cycle time
Keywords :
DRAM chips; application specific integrated circuits; cellular arrays; embedded systems; integrated circuit design; memory architecture; 0.35 micron; 150 MHz; 32 Mbit; DRAM module generator; DRAMGen; I/O-bit configurations; area penalty; cycle time; expandable cell array scheme; shared sense-amplifier scheme; Application specific integrated circuits; Decoding; Electronic switching systems; Energy consumption; Laboratories; Logic circuits; Random access memory; Semiconductor device testing; System testing; Systems engineering and theory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-4292-5
Type :
conf
DOI :
10.1109/CICC.1998.694982
Filename :
694982
Link To Document :
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