Hole filling: a novel delay reduction technique using selector logic

The proposed hole filling, contrary to the conventional method, makes use of paths with delay margins and provides a high-speed circuit by equalizing the delay margin of all paths. To achieve this delay reduction technique, we introduce a new concept named for the hole, which gives readily-usable information about the delay margins of a path. We also develop a new logic transformation method based on selector logic, which enables very flexible control of the path depth of a circuit. The benchmark test for a 32/64 bit adder and subtractor shows that hole filling reduces delay by about 50% without any area increase, compared to a conventional synthesis tool. Moreover, it is also confirmed that it is possible to reduce delay by about 10% for the logic (~10 K gates) of an actual microprocessor