Title :
Technology roadmap on SOC testing: issues on SOC testing in DSM era
Abstract :
Summary form only given. Deep sub-micron technology is rapidly leading to exceedingly complex, billion- transistor chips. By these technology evolutions, a system is integrated into a chip so called a system-on-a-chip (SOC). In order to bridge the productivity gap between available transistors and the ability to be designed in SOC, higher-level behavioral language and design re-use become more common. However, these techniques affect test methodologies and failure analysis of SOC
Keywords :
ULSI; application specific integrated circuits; automatic testing; failure analysis; fault diagnosis; integrated circuit testing; DSM era; SOC testing; design re-use; failure analysis; higher-level behavioral language; productivity gap; system-on-a-chip; technology roadmap; test methodologies; Analog circuits; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Design for testability; Failure analysis; Logic testing; System-on-a-chip;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982493
