Title :
Techniques to remove false paths in statistical static timing analysis
Author :
Tsukiyama, Shuji ; Tanaka, Masakazu ; Fukui, Masahiro
Author_Institution :
Dept. of EECE, Chuo Univ., Tokyo, Japan
Abstract :
In this paper, we propose techniques to remove certain false paths in the calculation of the distribution of the maximum delay of a given CMOS combinatorial circuit, when distributions of interconnect delays and gate switching delays of the circuit are given. Such a calculation is called the statistical static timing analysis, and the removal of false paths is important, since only the delays of true paths are to be analyzed in the static timing analysis
Keywords :
CMOS logic circuits; circuit analysis computing; combinational circuits; delays; timing; CMOS combinatorial circuit; false paths removal techniques; gate switching delays; interconnect delays; maximum delay distribution; statistical static timing analysis; Delay effects; Delay estimation; Integrated circuit interconnections; Large scale integration; Logic; Switching circuits; Timing; Uncertainty; Very large scale integration; Yield estimation;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982494
