Title :
Reconfigurable architecture of AVC/H.264 integer transform
Author :
Luczak, Adam ; Stepniewska, Marta
Author_Institution :
Div. of Multimedia Telecommun. & Radioelectron., Poznan Univ. of Technol., Poznan, Poland
Abstract :
The paper presents an original reconfigurable architecture of inverse integer transformation for H.264/AVC decoder. Proposed design can perform integer 4×4, 8×8 and Hadamard inverse transform including inverse quantization process as well. The design exploits pipelined architecture and supports FPGA devices. Simulation result indicates that proposed structure is characterized by low implementation cost and high efficiency. Final synthesis and test has been made for Xilinx Virtex family devices.
Keywords :
Hadamard transforms; field programmable gate arrays; inverse transforms; quantisation (signal); reconfigurable architectures; video coding; AVC-H.264 integer transform; FPGA devices; H.264-AVC decoder; Hadamard inverse transform; Xilinx Virtex family devices; inverse integer transformation; inverse quantization; pipelined architecture; reconfigurable architecture; Abstracts; IEC standards; Quantization (signal); Read only memory; Transforms; Video coding;
Conference_Titel :
Signal Processing Conference, 2006 14th European
Conference_Location :
Florence
